8086 Microprocessor Notes | COM SPPU 2024 Pattern

Introduction to the 16-Bit Microprocessor

A microprocessor is the central processing unit (CPU) of a computer built on a single integrated circuit chip. It controls all components, performs mathematical calculations, and executes programmatic instructions.

The Intel 8086 is a milestone in computing history. Released as a 16-bit microprocessor, it expanded upon older 8-bit designs like the 8085. A "16-bit" architecture means that its internal arithmetic logic unit, registers, and data instructions process 16 bits of information simultaneously. The 8086 introduced features like parallel processing pipelines and memory segmentation that enabled modern computing systems to thrive.

Key Features of the 8086 Microprocessor

16-Bit Architecture: It has an internal 16-bit Data Bus, meaning it can transfer 16 bits of data in a single cycle.
20-Bit Address Bus: With 20 address lines, the 8086 can access up to 2 raised to the power of 20 unique memory locations. This gives it a maximum physical memory capacity of exactly 1 Megabyte (1 MB).
Pipelining Mechanism: It fetches instructions from memory while executing the current instruction, significantly accelerating processing throughput.
Dual Mode Operation: It operates in two distinct functional modes: Minimum Mode (for single-processor setups) and Maximum Mode (for multi-processor environments).
Clock Frequencies: Depending on the specific version, it operates at speeds ranging between 5 MHz and 10 MHz.

8086 Internal Architecture

The internal design of the 8086 is uniquely divided into two independent functional modules working in parallel. This structural split ensures that the CPU does not waste processing cycles waiting for code to fetch from memory.

+-------------------------------------------------------------+
|               8086 MICROPROCESSOR INTERNAL DESIGN           |
+-------------------------------------------------------------+
|  BUS INTERFACE UNIT (BIU)     |  EXECUTION UNIT (EU)        |
|                               |                             |
|  - Segment Registers          |  - Control Circuitry        |
|    (CS, DS, SS, ES)           |  - Instruction Decoder      |
|  - Instruction Pointer (IP)   |  - Arithmetic Logic Unit    |
|  - 6-Byte Instruction Queue   |  - General Purpose Registers|
|  - Physical Address Adder     |  - Flag Register            |
+-------------------------------------------------------------+

Bus Interface Unit (BIU)

The Bus Interface Unit handles all external communication between the processor and the outside memory or peripheral devices. It is responsible for sending out memory addresses, fetching instruction codes, and reading/writing system data.

Key Elements of the BIU

Instruction Queue: A 6-byte storage container that holds up to six bytes of pre-fetched instruction code. While the execution unit is busy processing a command, the BIU pulls subsequent instructions from memory into this buffer. This overlap is known as pipelining.
Segment Registers: Four specialized 16-bit registers used to maintain the segmented structure of the memory system (Code, Data, Stack, and Extra segments).
Instruction Pointer (IP): A 16-bit register that holds the memory offset address of the next instruction code to be fetched.
Address Generation Circuit: A hardware adder that converts 16-bit register addresses into the 20-bit physical addresses needed to access physical memory.

Execution Unit (EU)

The Execution Unit is responsible for interpreting and running the instructions fetched by the BIU. It does not connect directly to the outside system buses; instead, it receives its data streams directly from the BIU instruction queue.

Key Elements of the EU

Control Circuitry: Coordinates and directs all processing operations inside the execution core.
Instruction Decoder: Translates raw instruction code bytes into fine hardware execution signals.
Arithmetic Logic Unit (ALU): The mathematical core that executes 8-bit and 16-bit operations, including addition, subtraction, AND, OR, and bit shifts.
Working Registers: A set of general-purpose and pointer registers used to hold temporary values, memory offsets, and counters.
Flag Register: A 16-bit status tracker that reflects the results of recent mathematical actions.

Hinglish Explanation: 8086 architecture ko do bhaago mein baanta gaya hai: BIU aur EU. BIU ka kaam hai bahar se data aur instructions ko lekar aana aur unhe 6-byte ki Queue mein store karna. EU ka kaam hai us Queue se instruction lena, use decode karna aur ALU ki madad se execute karna. Dono ek saath kaam karte hain jisse system ki speed badh jaati hai.

Pin Diagram and Functionality

The 8086 is housed in a standard 40-pin Dual In-line Package (DIP). Understanding its pin layout helps clarify how it interfaces with system hardware.

                     +---_---+
                GND | 1    40| VCC (+5V)
            AD14    | 2    39| AD15
            AD13    | 3    38| A16/S3
            AD12    | 4    37| A17/S4
            AD11    | 5    36| A18/S5
            AD10    | 6    35| A19/S6
             AD9    | 7    34| BHE'/S7
             AD8    | 8    33| MN/MX'
             AD7    | 9    32| RD'
             AD6    | 10   31| HOLD (RQ'/GT0')
             AD5    | 11   30| HLDA (RQ'/GT1')
             AD4    | 12   29| WR'  (LOCK')
             AD3    | 13   28| M/IO'(S2')
             AD2    | 14   27| DT/R'(S1')
             AD1    | 15   26| DEN' (S0')
             AD0    | 16   25| ALE  (QS0)
            NMl     | 17   24| INTA'(QS1)
            INTR    | 18   23| TEST'
            CLK     | 19   22| READY
                GND | 20   21| RESET
                    +-------+

Pin Descriptions and Signal Categories

Multiplexed Address and Data Lines (AD0 - AD15)

These lines are multiplexed, meaning they share functions to conserve physical pins. During the first part of a memory cycle, pins 2 through 16 behave as address lines (A0 to A15) to locate memory blocks. During subsequent phases, they transition into bidirectional data lines (D0 to D15) to transfer information.

Multiplexed Address and Status Lines (A16/S3 - A19/S6)

These are the upper four address lines needed to complete the 20-bit address bus. After the initial address phase, they switch roles to display status updates (S3 to S6) regarding internal segment access and interrupt management.

Power and Ground Controls

VCC (Pin 40): Receives the primary +5V direct current power supply.
GND (Pins 1 and 20): Ground references for the chip's electrical circuits.

Controlling Clock and Reset Signals

CLK (Pin 19): Receives the external timing clock wave that synchronizes all internal microprocessor operations.
RESET (Pin 21): Forces the processor to terminate current loops and restart. It clears the status registers and sets the instruction pointer to a predictable initial boot state.

External Interrupt Pins

INTR (Pin 18): Interrupt Request line. Hardware peripherals use this pin to signal that they need attention. It can be disabled or masked via software.
NMI (Pin 17): Non-Maskable Interrupt. A high-priority interrupt pin reserved for critical hardware failures or power emergencies; it cannot be ignored by software.

Specialized System Control Pins

BHE'/S7 (Pin 34): Bus High Enable. An active-low signal used to validate data transfers across the upper half of the system data bus (D8 to D15).
RD' (Pin 32): Read signal. An active-low pin indicating that the CPU is reading data from memory or an I/O device.
READY (Pin 22): Used by slow memory devices to notify the CPU that they need more time to complete a data transfer. If this signal is low, the processor enters wait states.
TEST' (Pin 23): Used in conjunction with the WAIT instruction to synchronize the processor with external math co-processors.

Mode Selection: Minimum vs. Maximum Mode (MN/MX')

MN/MX' (Pin 33): Mode Selection Pin. If wired directly to +5V (Logic High), the microprocessor runs in Minimum Mode, where it generates all bus control signals internally. If tied to ground (Logic Low), it operates in Maximum Mode, delegating complex bus control tasks to an external 8288 support chip. Pins 24 through 31 change their functions entirely based on the state of this pin.

Programmer's Model of the 8086: Registers

The programmer’s model defines the internal registers accessible to assembly software developers. The 8086 contains fourteen distinct 16-bit registers, categorized by their primary functional roles.

+-----------------------------------------------------------------+
|                    8086 REGISTER ARCHITECTURE                   |
+-----------------------------------------------------------------+
| GENERAL PURPOSE REGISTERS      | POINTERS AND INDEX REGISTERS   |
|  AX  [  AH  ] [  AL  ]         |  SP  (Stack Pointer)           |
|  BX  [  BH  ] [  BL  ]         |  BP  (Base Pointer)            |
|  CX  [  CH  ] [  CL  ]         |  SI  (Source Index)            |
|  DX  [  DH  ] [  DL  ]         |  DI  (Destination Index)       |
+--------------------------------+--------------------------------+
| SEGMENT REGISTERS              | CONTROL REGISTERS              |
|  CS  (Code Segment)            |  IP  (Instruction Pointer)     |
|  DS  (Data Segment)            |  FLAGS                         |
|  SS  (Stack Segment)           |                                |
|  ES  (Extra Segment)           |                                |
+-----------------------------------------------------------------+

General Purpose Registers

These four 16-bit registers can hold variables, math operands, or address components. Each can also be split into two independent 8-bit registers: a High byte (H) and a Low byte (L).

AX (Accumulator Register): Divided into AH and AL. It is the preferred register for arithmetic operations, logical manipulation, and Input/Output data transfers.
BX (Base Register): Divided into BH and BL. It often holds base addresses pointing to data tables in memory.
CX (Count Register): Divided into CH and CL. It serves as an automatic loop counter for repetition blocks and bit-shift counters.
DX (Data Register): Divided into DH and DL. Used in multiplication and division operations, and to hold I/O port addresses during complex input/output instructions.

Pointers and Index Registers

These registers point to specific memory offset addresses within data segments. They cannot be split into 8-bit components.

SP (Stack Pointer): Holds the offset address of the current top item within the Stack segment.
BP (Base Pointer): Primarily used to pass variables and parameters across stack frames.
SI (Source Index): Points to the source data stream during string copy or manipulation instructions.
DI (Destination Index): Points to the destination memory target for string operations.

Segment Registers

The 8086 uses memory segmentation, dividing the 1 MB address space into logical blocks of up to 64 KB each. Four segment registers define where these active blocks begin in physical memory:

CS (Code Segment): Points to the base location of the executable program code.
DS (Data Segment): Points to the primary storage location for program variables and data constants.
SS (Stack Segment): Reserves a region of memory for storing return addresses and temporary subroutine data.
ES (Extra Segment): An additional data segment area, primarily used for large string operations.

Flag Register (Status Register)

The Flag register is a 16-bit register containing nine active status or control bits. The remaining seven bits are undefined.

 Bit:  15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
       ---------------------------------------------------------------
      |   |   |   |   | O | D | I | T | S | Z |   | A |   | P |   | C |
       ---------------------------------------------------------------

Status Flags

Carry Flag (CF): Set to 1 if an arithmetic operation generates a carry out of the most significant bit.
Parity Flag (PF): Set to 1 if the lower 8 bits of a result contain an even number of 1s.
Auxiliary Carry Flag (AF): Set to 1 if a carry occurs from bit 3 to bit 4 during binary coded decimal (BCD) math.
Zero Flag (ZF): Set to 1 if the result of an operation is zero.
Sign Flag (SF): Set to 1 if the highest bit of a result is 1, indicating a negative number.
Overflow Flag (OF): Set to 1 if a signed arithmetic calculation exceeds the capacity of the target register.

Control Flags

Trap Flag (TF): Enables single-step debugging mode. When set to 1, the processor interrupts execution after every instruction so a programmer can inspect variables.
Interrupt Enable Flag (IF): Controls whether external maskable interrupts (via the INTR pin) are recognized (1) or ignored (0).
Direction Flag (DF): Controls string processing direction. When set to 1, string addresses auto-decrement (right to left). When cleared to 0, they auto-increment (left to right).

Physical Address Generation in the 8086

Because the 8086 uses 16-bit internal registers but requires a 20-bit address to access its 1 MB physical memory space, it uses a segment-plus-offset calculation model.

To generate a 20-bit physical address, the Bus Interface Unit shifts the 16-bit segment register value left by 4 binary bits (equivalent to multiplying by 16, or adding a hex 0 to the end) and adds the 16-bit offset address.

Physical Address = (Segment Register Value × 16) + Offset Address

Addressing Calculation Example

Suppose the Code Segment (CS) register holds the value 2000H and the Instruction Pointer (IP) contains 1234H. The physical address of the next instruction is calculated as follows:

  Segment Address (CS):    2000H  --> Shift left =  20000H
+ Offset Address  (IP):                             01234H
----------------------------------------------------------
= Physical Address:                                 21234H

Hinglish Explanation: 8086 ke andar registers 16-bit ke hote hain, par humein memory access karne ke liye 20-bit ka address chahiye hota hai. Iske liye processor Segment address ke aage ek zero laga deta hai (ya use 16 se multiply karta hai) aur phir usmein Offset address ko jod (add) deta hai. Jaise 2000H ban jaata hai 20000H, aur usme 1234H add karne par 21234H ka exact location milta hai.

Addressing Modes of the 8086

Addressing modes define how the microprocessor locates the operands needed by an instruction. The 8086 provides several addressing modes to balance performance and programming flexibility.

Immediate Addressing Mode

The data operand is specified directly inside the instruction code itself. No memory or register lookups are required to determine the value.

Example: MOV AX, 0025H (Loads the constant hexadecimal value 0025H directly into register AX).

Register Addressing Mode

The data is stored inside an internal microprocessor register. The instruction specifies which register to read from or write to.

Example: MOV CX, BX (Copies the 16-bit contents of register BX into register CX).

Direct Addressing Mode

The instruction explicitly includes the 16-bit offset address of the data, which is enclosed in square brackets. By default, this offset points to a location within the Data Segment (DS).

Example: MOV AX, [5000H] (Computes the physical target location using DS and the offset 5000H, then copies the data found there into AX).

Register Indirect Addressing Mode

The offset address of the operand is stored within a pointer or base register (BX, SI, or DI). The instruction points to that register to discover where the final data resides.

Example: MOV AX, [BX] (Looks at the address value stored inside BX, goes to that memory location, and loads its contents into AX).

Indexed Addressing Mode

The operand's offset address is calculated by adding a fixed displacement value to the contents of an index register (SI or DI).

Example: MOV AX, [SI + 20H] (Adds 20H to the value inside SI to find the target memory offset).

Based Addressing Mode

The offset address is calculated by adding a fixed displacement value to the contents of a base register (BX or BP).

Example: MOV CX, [BX + 12H] (Adds 12H to the value inside BX to determine the target memory address).

Based Indexed Addressing Mode

The address offset is calculated by adding the contents of a base register (BX or BP) to the contents of an index register (SI or DI).

Example: MOV AX, [BX + SI] (Adds the values inside BX and SI together to find the final memory offset).

8086 Instruction Set

The instruction set defines the complete library of commands that the 8086 microprocessor can interpret and execute. These instructions are grouped by functional category.

1. Data Movement Instructions

These instructions copy data between registers, memory locations, and input/output ports. They do not alter the system status flags.

MOV: Copies data from a source operand to a destination operand.
- Syntax: MOV Destination, Source
- Example: MOV AX, BX
PUSH: Decrements the stack pointer and copies the specified operand onto the top of the stack.
POP: Copies the item at the top of the stack into a destination register, then increments the stack pointer.
XCHG: Swaps the contents of two registers, or a register and a memory location.

2. Arithmetic Instructions

These commands perform mathematical operations on binary or decimal values and update the status flags based on the result.

ADD: Adds a source operand to a destination operand, storing the result in the destination.
- Example: ADD AX, 1000H
SUB: Subtracts the source operand from the destination operand.
- Example: SUB BX, CX
MUL: Performs unsigned multiplication of an operand by the accumulator (AL or AX).
DIV: Performs unsigned division of the accumulator by a specified divisor operand.
INC / DEC: Increments (adds 1) or decrements (subtracts 1) a register or memory location.

3. Logic Instructions

These instructions execute bitwise operations on operands, which is useful for testing, masking, or clearing specific bits.

AND: Performs a bitwise logical AND operation. Often used to clear or mask specific bits.
- Example: AND AL, 0FH (Clears the upper 4 bits of AL).
OR: Performs a bitwise logical OR operation. Often used to set specific bits to 1.
XOR: Performs an exclusive-OR operation. A common use case is clearing a register by XORing it with itself (XOR AX, AX).
NOT: Inverts all bits of the specified operand (1's complement).
SHL / SHR: Shifts the bits of an operand left or right by a specified count.

4. Control Transfer Instructions

These instructions alter the sequential execution flow of a program by jumping to a different target address. They enable conditional loops and subroutines.

JMP: An unconditional jump that forces the program counter to move to a new label destination.
JE / JNE: Conditional jumps that redirect execution only if the Zero Flag indicates equality (JE) or inequality (JNE).
JC / JNC: Jumps based on whether the Carry Flag is set (JC) or clear (JNC).
CALL / RET: CALL saves the current return address onto the stack and jumps to a subroutine. RET pops that address back into the instruction pointer to resume normal program flow.

5. String Instructions

These specialized instructions manipulate arrays or strings of text bytes/words efficiently in a single operation. They use the SI and DI registers to track memory targets.

MOVSB / MOVSW: Copies a byte (MOVSB) or word (MOVSW) from the source string location (pointed to by SI) to the destination string location (pointed to by DI).
CMPS: Compares the contents of two string elements to find differences.
SCAS: Scans a string to find a specific character match that equals the value inside the accumulator.
REP: A prefix that repeats the associated string instruction until the CX register reaches zero.

6. Input / Output (I/O) Instructions

These commands transfer data between the microprocessor's accumulator register and external hardware devices or peripherals.

IN: Inputs a byte or word from a specified hardware port into the AL or AX register.
- Example: IN AL, 80H (Reads data from hardware port 80H into AL).
OUT: Outputs a byte or word from the AL or AX register to an external hardware port.

7. Flag Control Instructions

These instructions allow a programmer to directly set, clear, or invert specific bits inside the Flag register.

CLC: Clears the Carry Flag (CF = 0).
STC: Sets the Carry Flag (CF = 1).
CMC: Complements (inverts) the state of the Carry Flag.
CLD / STD: Clears (CLD) or sets (STD) the Direction Flag to control string processing behavior.

8. Process Control Instructions

These commands coordinate the microprocessor's operation with external components or handle synchronization in multi-processor environments.

HLT: Halts the processor. The CPU enters an idle state until an external hardware interrupt or system reset occurs.
WAIT: Forces the processor to enter an idle state while checking the status of the TEST' pin. It stays paused until the pin goes low.
LOCK: A prefix that prevents external processors from taking control of the system bus while the current instruction executes.

Technical Summary and Key Takeaways

Pipelined Architecture: The 8086 balances processing workloads by dividing tasks between the Bus Interface Unit (BIU) and the Execution Unit (EU), allowing instruction pre-fetching via a 6-byte queue.
Memory Segmentation Benefit: It expands its physical addressing reach to 1 MB using a 20-bit bus address system. This calculation combines a shifted 16-bit segment base value with a 16-bit register offset.
Flexible Access Choices: Seven distinct addressing modes allow developers to access data constants immediately, query registers directly, or compute complex memory offsets using combinations of based and indexed registers.
Comprehensive Command Library: The robust instruction set provides dedicated tools for data movement, arithmetic, logical bit masking, string array manipulation, and low-level input/output mapping.

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Unit 3 – Introduction to 8086 Microprocessor | SPPU 2024 Pattern